DesignCon 2010 experience

In early February I have attended DesignCon 2010 conference. It gave me a new insight into the state of the industry and understanding of the trends in the nearest future. In this paper I would like to share some of my conference experience.

The DesignCon is a most comprehensive technical forum directed specifically toward engineers. It identifies industry directions and serves as major informational and educational tool for engineers. It covers several topics. One of the major focuses of this forum is the state-of-the-art interface technologies, design and test methodologies, standards, tools, future developments and so on.

Electronics industry is on the verge of bandwidth explosion
All keynote speakers that have shown their view on the position of the industry, including PCB manufacturer Sanmina-SCI’s CEO Jure Sola, chip manufacturer Virage Logic’s president and CEO Alex Shubat, Altera’s VP of Product and Corporate Marketing Vince Hu, as well as multiple other speakers familiar with the state of the electronics industry, have identified the imminence of the bandwidth demand explosion. They have cited the change in the cultural and social habits when virtual reality and virtual interaction is becoming more enthralling for young people. These changes are accompanied by sharp increase in bandwidth demand. Thus, the use and exchange of video files requiring much more bandwidth in both directions is rising and also proliferation of mobile devices that provide full Internet access. These cultural changes clearly demand higher IO rates and, of course, the increase in the data rates used in IO and backplane interfaces. As a reflection of these trends the IEEE committee is developing a new Ethernet standard, 802.3ba, that defines 40G and 100Gbps interfaces.

Similar message could be heard at the discussion of the panel “Meeting Chip to Chip I/O Demands of 100G and Beyond Line Cards”. Among others this panel has included several representatives from chip manufacturers, such as Qinghua Bill Chen – Senior Engineering Manager, Cisco Systems; Michael Miller – Vice President, System Applications, MoSys, Inc. and Anthony Torza – Staff System Architect, Xilinx. One of the main issues for chip manufacturers at this point is the imbalance between the tremendous increase in bandwidth demand due to the IO speed rise and inadequate memory access speed. They are considering the use of very high-rate differential line busses for memory access.

All these developments are pointing to the changes that system interfaces are about to undergo in the next few years. Currently the industry’s bulk of interface baud rates are in the region of 2.5Gb – 3.125Gb with few manufacturers working in the 10Gbps domain. The DesignCon speakers have shown the tendency for next year: the shift toward 10Gb – 25Gb data rates is clearly at our door steps.

New challenges, new methodologies
The DesignCon conference has produced several tutorials with great educational and informational values. One of them, “Quality of High Frequency Measurements: Practical Examples, Theoretical Foundations, and Successful Techniques that Work Past the 40GHz Realm” has stated in its summary: “It may seem only a small step from 3 Gbps to 10Gbps but in terms of measurement quality and simulations this is where the real work begins and it is no longer just a few that face this challenge. Mainstream PCIE and HyperTransport interfaces are moving beyond 5Gbps, DDR memory is pushing past 3Gbps, and XDR is pushing 10 Gbps.”

The higher data rates present new challenges and new techniques to be used. A great number of papers at DesignCon were dedicated to analysis methodologies, simplification of used tools and analysis time reduction. These new challenges were addressed with innovative approaches and solutions. In many cases the presentations outlined the techniques and methodologies established for analysis of applications with data rates at 10Gb and above.

Test challenges
For a number of years the DesignCon assembles a panel that discusses issues of interface design verification. This year topic was: “The Case of the Shrinking Eye: How Do We Keep Our Shrinking Eyes Open in the Face of Rising Signal Complexity?” The panel is set up as a debate between the measurement equipment design engineers and components design engineers. The main issue is that integration of line equalization circuits into transceiver devices prevents access to the cleaned signal. As the data rates approach 10Gbps the eye of the signal that reaches receiver is completely closed even on interconnects with relatively simple geometry and since the Eye Diagram or BER measurements on such interface would not tell us much about interface performance this discussion always ends up in a heated argument. The transceiver designers (Mike Li – Altera) see the solution in incorporation of special measuring devices inside the receiver that clearly increases the cost of component, its size and power consumption. Test equipment engineers still have no clear solution. The emphasis of the test equipment manufacturers is on the ability to achieve increasingly higher bandwidth for measurement accuracy, incorporation of mathematical engine for signal processing like conversion from one domain into another, de-embedding of the significant circuit from the measured channel and so on.

Simulation trends
The testing difficulties that were discussed above point out to a new and critical role of simulation analysis. DesignCon 2010 has identified once more that simulation is becoming a main approach for interface verification and has shown new trends in simulation analysis. A large number of papers have discussed how the type and quality of models determine the accuracy of simulation analysis is. The lump components models used by behavior simulators or HSPICE (W-element) are incapable of meeting the needs of the multi-gigabit simulations. The acceptable alternatives are S-parameter models or EM analysis. Of course the full EM analysis is very time consuming. Therefore, the S-parameter models have become a de-facto standard. The use of S-parameter models, however, requires detail understanding of models’ properties, their limitations and how to deal with these limitations. The presentations of the Technical Forum “Quality of High Frequency Measurements: Practical Examples, Theoretical Foundations, and Successful Techniques that Work Past the 40GHz Realm” have provided an interesting insight into S-parameter models passivity, causality and reciprocity issues.

The DesignCon papers have also paid a lot attention to statistical analysis methodologies and have shown that statistical simulation methodologies have become an important part of Signal Integrity engineer arsenal and are incorporated into the new releases of multiple signal integrity tools. The major reason that these techniques are so important is their speed. The statistical methods bring the speed of behavioral simulations into the realm of multi-gigabit applications.