Differential Line Skew

One of the frequently asked questions is "what is the allowed skew between the traces in a differential pair". Sometimes the skew requirements for a differential interface are provided in its specifications. Thus, the TIA/EIA-644 or LVDS standard actually limits the maximum difference of the trace lengths within a differential pair link to 0.100". However, in majority of the high-speed interfaces the skew between lines in differential pair is not defined. Therefore, the question is what other parameters that are specified may be used in order to determine the skew within a differential pair.

Let us consider the effect of a trace skew in a differential pair. Assuming that there is no transmitter skew the signal on one branch of the differential pair will reach receiver before or after the signal on the other branch.

Figure 1. Signal distortion due differential traces skew

As the Figure 1 shows the difference of trace length in a differential pair produces distortion of the differential signal. This distortion clearly indicates that for the time that it takes the signal on the longer branch to catch up with the signal on the shorter one the signal from the differential mode switches into the common mode (when both branches of the differential line have the same potential) of propagation. Obviously, this switch distorts the signal and affects its integrity. Understanding the type of the distortion and how one may estimate the effect of the skew on differential signal may help us to address the original question and estimate the interface tolerance to the skew of differential traces.

Let us now look into how the parameters of interface media are specified according to the interface standards. The Figure 2 shows and example of transmitter and receiver specifications in form of the Eye Diagram Pattern masks as provided in the PCI Express standard for 2.5Gbps application. These signal masks define the signal amplitude and phase limits at the receiver and transmitter. The phase limits specified by these masks identify the allowed phase deviation of the signal and define the time window when signal shall be within its required range. The signal's phase deviation is called jitter and the jitter parameter is one of the major parameters defined for the high-speed interfaces. Obviously, the increase of jitter reduces the time available for the signal detection.

As it is illustrated in Figure 1 the length difference of differential traces increases the interface jitter. Of course, for the case of very high-speed interfaces, when the rise and fall times of the signal become comparable to the signal cycle the jitter increase also reduces the signal amplitude, thus closing the signal eye in the Receiver's input Eye Diagram in horizontal and vertical directions.

Figure 2. Interface performance specification

The speculation in Figure 2 allows us to define the methodology for analysis of trace length difference in a differential pair as a part of the interface jitter analysis. There are multiple factors that may affect the interface jitter performance: transmitter output jitter, interface media loss, Inter Symbol Interference (ISI), crosstalk, other noise sources like Simultaneous Switching Noise (SSN) and so on. Once the jitter budget is defined as a part of the standard and all other sources of jitter are defined the trace skew requirements may be addressed as well. In some cases the limitations of the physical design, trace length tolerance, connector pins length variations and so on may define the limit for the interface lines skew. In such cases the other noise sources and interface length should be controlled in order to achieve the overall interface jitter requirements as defined in the interface specification.

There are some applications where skew within differential pair of interface signals is indirectly specified via different parameters. One of the important examples of such specifications is the Ethernet standard definition of the interface between the PHY module and the Ethernet cabling plant – MDI (Medium Dependent Interface). The 1000BASE-T requirements define MDI impedance balance (section 40.8.3.2, IEEE Std. 802.3-2005) as follows:

By calculating the impedance imbalance due to the MDI trace length difference in differential pairs utilizing the lumped parameters of the traces unit length one may determine whether design of the 1000BASE-T MDI section meets the requirement that specified in the same section of the IEEE 802.3 Standard or determine the skew value that satisfies this requirement.