DesignCon 2010 experience

In early February I have attended DesignCon 2010 conference. It gave me a new insight into the state of the industry and understanding of the trends in the nearest future. In this paper I would like to share some of my conference experience.

The DesignCon is a most comprehensive technical forum directed specifically toward engineers. It identifies industry directions and serves as major informational and educational tool for engineers. It covers several topics. One of the major focuses of this forum is the state-of-the-art interface technologies, design and test methodologies, standards, tools, future developments and so on.

Electronics industry is on the verge of bandwidth explosion
All keynote speakers that have shown their view on the position of the industry, including PCB manufacturer Sanmina-SCI’s CEO Jure Sola, chip manufacturer Virage Logic’s president and CEO Alex Shubat, Altera’s VP of Product and Corporate Marketing Vince Hu, as well as multiple other speakers familiar with the state of the electronics industry, have identified the imminence of the bandwidth demand explosion. They have cited the change in the cultural and social habits when virtual reality and virtual interaction is becoming more enthralling for young people. These changes are accompanied by sharp increase in bandwidth demand. Thus, the use and exchange of video files requiring much more bandwidth in both directions is rising and also proliferation of mobile devices that provide full Internet access. These cultural changes clearly demand higher IO rates and, of course, the increase in the data rates used in IO and backplane interfaces. As a reflection of these trends the IEEE committee is developing a new Ethernet standard, 802.3ba, that defines 40G and 100Gbps interfaces.

Similar message could be heard at the discussion of the panel “Meeting Chip to Chip I/O Demands of 100G and Beyond Line Cards”. Among others this panel has included several representatives from chip manufacturers, such as Qinghua Bill Chen – Senior Engineering Manager, Cisco Systems; Michael Miller – Vice President, System Applications, MoSys, Inc. and Anthony Torza – Staff System Architect, Xilinx. One of the main issues for chip manufacturers at this point is the imbalance between the tremendous increase in bandwidth demand due to the IO speed rise and inadequate memory access speed. They are considering the use of very high-rate differential line busses for memory access.

All these developments are pointing to the changes that system interfaces are about to undergo in the next few years. Currently the industry’s bulk of interface baud rates are in the region of 2.5Gb – 3.125Gb with few manufacturers working in the 10Gbps domain. The DesignCon speakers have shown the tendency for next year: the shift toward 10Gb – 25Gb data rates is clearly at our door steps.

New challenges, new methodologies
The DesignCon conference has produced several tutorials with great educational and informational values. One of them, “Quality of High Frequency Measurements: Practical Examples, Theoretical Foundations, and Successful Techniques that Work Past the 40GHz Realm” has stated in its summary: “It may seem only a small step from 3 Gbps to 10Gbps but in terms of measurement quality and simulations this is where the real work begins and it is no longer just a few that face this challenge. Mainstream PCIE and HyperTransport interfaces are moving beyond 5Gbps, DDR memory is pushing past 3Gbps, and XDR is pushing 10 Gbps.”

The higher data rates present new challenges and new techniques to be used. A great number of papers at DesignCon were dedicated to analysis methodologies, simplification of used tools and analysis time reduction. These new challenges were addressed with innovative approaches and solutions. In many cases the presentations outlined the techniques and methodologies established for analysis of applications with data rates at 10Gb and above.

Test challenges
For a number of years the DesignCon assembles a panel that discusses issues of interface design verification. This year topic was: “The Case of the Shrinking Eye: How Do We Keep Our Shrinking Eyes Open in the Face of Rising Signal Complexity?” The panel is set up as a debate between the measurement equipment design engineers and components design engineers. The main issue is that integration of line equalization circuits into transceiver devices prevents access to the cleaned signal. As the data rates approach 10Gbps the eye of the signal that reaches receiver is completely closed even on interconnects with relatively simple geometry and since the Eye Diagram or BER measurements on such interface would not tell us much about interface performance this discussion always ends up in a heated argument. The transceiver designers (Mike Li – Altera) see the solution in incorporation of special measuring devices inside the receiver that clearly increases the cost of component, its size and power consumption. Test equipment engineers still have no clear solution. The emphasis of the test equipment manufacturers is on the ability to achieve increasingly higher bandwidth for measurement accuracy, incorporation of mathematical engine for signal processing like conversion from one domain into another, de-embedding of the significant circuit from the measured channel and so on.

Simulation trends
The testing difficulties that were discussed above point out to a new and critical role of simulation analysis. DesignCon 2010 has identified once more that simulation is becoming a main approach for interface verification and has shown new trends in simulation analysis. A large number of papers have discussed how the type and quality of models determine the accuracy of simulation analysis is. The lump components models used by behavior simulators or HSPICE (W-element) are incapable of meeting the needs of the multi-gigabit simulations. The acceptable alternatives are S-parameter models or EM analysis. Of course the full EM analysis is very time consuming. Therefore, the S-parameter models have become a de-facto standard. The use of S-parameter models, however, requires detail understanding of models’ properties, their limitations and how to deal with these limitations. The presentations of the Technical Forum “Quality of High Frequency Measurements: Practical Examples, Theoretical Foundations, and Successful Techniques that Work Past the 40GHz Realm” have provided an interesting insight into S-parameter models passivity, causality and reciprocity issues.

The DesignCon papers have also paid a lot attention to statistical analysis methodologies and have shown that statistical simulation methodologies have become an important part of Signal Integrity engineer arsenal and are incorporated into the new releases of multiple signal integrity tools. The major reason that these techniques are so important is their speed. The statistical methods bring the speed of behavioral simulations into the realm of multi-gigabit applications.

Differential Line Skew

One of the frequently asked questions is "what is the allowed skew between the traces in a differential pair". Sometimes the skew requirements for a differential interface are provided in its specifications. Thus, the TIA/EIA-644 or LVDS standard actually limits the maximum difference of the trace lengths within a differential pair link to 0.100". However, in majority of the high-speed interfaces the skew between lines in differential pair is not defined. Therefore, the question is what other parameters that are specified may be used in order to determine the skew within a differential pair.

Let us consider the effect of a trace skew in a differential pair. Assuming that there is no transmitter skew the signal on one branch of the differential pair will reach receiver before or after the signal on the other branch.

Figure 1. Signal distortion due differential traces skew

As the Figure 1 shows the difference of trace length in a differential pair produces distortion of the differential signal. This distortion clearly indicates that for the time that it takes the signal on the longer branch to catch up with the signal on the shorter one the signal from the differential mode switches into the common mode (when both branches of the differential line have the same potential) of propagation. Obviously, this switch distorts the signal and affects its integrity. Understanding the type of the distortion and how one may estimate the effect of the skew on differential signal may help us to address the original question and estimate the interface tolerance to the skew of differential traces.

Let us now look into how the parameters of interface media are specified according to the interface standards. The Figure 2 shows and example of transmitter and receiver specifications in form of the Eye Diagram Pattern masks as provided in the PCI Express standard for 2.5Gbps application. These signal masks define the signal amplitude and phase limits at the receiver and transmitter. The phase limits specified by these masks identify the allowed phase deviation of the signal and define the time window when signal shall be within its required range. The signal's phase deviation is called jitter and the jitter parameter is one of the major parameters defined for the high-speed interfaces. Obviously, the increase of jitter reduces the time available for the signal detection.

As it is illustrated in Figure 1 the length difference of differential traces increases the interface jitter. Of course, for the case of very high-speed interfaces, when the rise and fall times of the signal become comparable to the signal cycle the jitter increase also reduces the signal amplitude, thus closing the signal eye in the Receiver's input Eye Diagram in horizontal and vertical directions.

Figure 2. Interface performance specification

The speculation in Figure 2 allows us to define the methodology for analysis of trace length difference in a differential pair as a part of the interface jitter analysis. There are multiple factors that may affect the interface jitter performance: transmitter output jitter, interface media loss, Inter Symbol Interference (ISI), crosstalk, other noise sources like Simultaneous Switching Noise (SSN) and so on. Once the jitter budget is defined as a part of the standard and all other sources of jitter are defined the trace skew requirements may be addressed as well. In some cases the limitations of the physical design, trace length tolerance, connector pins length variations and so on may define the limit for the interface lines skew. In such cases the other noise sources and interface length should be controlled in order to achieve the overall interface jitter requirements as defined in the interface specification.

There are some applications where skew within differential pair of interface signals is indirectly specified via different parameters. One of the important examples of such specifications is the Ethernet standard definition of the interface between the PHY module and the Ethernet cabling plant – MDI (Medium Dependent Interface). The 1000BASE-T requirements define MDI impedance balance (section 40.8.3.2, IEEE Std. 802.3-2005) as follows:

By calculating the impedance imbalance due to the MDI trace length difference in differential pairs utilizing the lumped parameters of the traces unit length one may determine whether design of the 1000BASE-T MDI section meets the requirement that specified in the same section of the IEEE 802.3 Standard or determine the skew value that satisfies this requirement.

Differential Impedance

Nowadays it is not unusual to use differential signaling. Majority of high-speed interfaces are using the differential signaling. However, many engineers are not clear on the nature of one of the major parameters of differential lines – the differential characteristic impedance.

Let us now consider the specific aspects of signal propagation on differential transmission line. The signals on two wires of a differential line may have any of the infinite number of possible relationships. If the signal and signal-not lines are coupled the signals on both lines will affect each other and distort their waveforms. There are two modes of signals relationship, however, when signals reach their destinations undistorted: the differential or odd mode and common or even mode. In case of differential mode the signals are exactly 180 degree out of phase, and in case of common mode the signals are exactly in phase. If the branches of differential line are geometrically slightly different the differential signal will arrive distorted to destination. That means that geometry of lines defines the modes that will carry the signals to the end undistorted. For practical purposes we will consider symmetrical or balanced lines.

In case of the single ended lines we want to minimize the mutual components in order to reduce the effect of one line on another, or crosstalk. For differential application the mutual parameters are defined and should be controlled. We may start with general equations that govern performance of two lines with mutual capacitance and inductance.

The first two equations express voltage as a function of current with help of self and mutual inductances.

V1 = L1 * dI1/dt + Lm * dI2/dt (1a)
V2 = Lm * dI1/dt + L2 * dI2/dt (1b)

The second two equations represent current as a function of voltage with help of capacitances from the lines to reference plane and between the lines themselves.

I1 = C1 * dV1/dt + Cm * d(V1 - V2)/dt

I2 = C2 * dV2/dt + Cm * d(V2 - V1)/dt
or
I1 = (C1 + Cm) * dV1/dt - Cm * dV2/dt (2a)
I2 = - Cm * dV1/dt + (C2 + Cm) * dV2/dt (2b)

Where:
L1 and L2 are respective self-inductances of each branch of differential line
Lm is a mutual inductance between two branches of differential line
C1 and C2 are respective self-capacitances of each branch of differential line to ground
Cm is a mutual capacitance between two branches of differential line

Now we may address the Odd or Differential signal propagation mode, where I1 = -I2; V1 = -V2. From equations (1) and (2) for one branch of differential lines:

V1 = L1 * dI1/dt - Lm * dI1/dt => V1 = jw(L1-Lm)*I1
I1 = (C1 + Cm) * dV1/dt + Cm * dV1/dt => I1 = jw(C1+2Cm)*V1

From these two equations it is easy to obtain the relationship between the voltage and current, which represents the characteristic line impedance of one branch of differential line and that is called an Odd characteristic line impedance:

Zodd = V1/I1 = Ö[(L1 – Lm)/(C1 + 2Cm)]

Also considering that we are dealing with symmetrical lines and, therefore, L1 = L2 = L and C1 = C2 = C, than:

Zodd = Ö[(L – Lm)/(C + 2Cm)] (3)

In order to determine the differential characteristic impedance we may write equations for both branches of the differential line:

V1 = Zodd * I1
V2 = Zodd * I2

Considering that differential voltage between the signals on branches of differential line is the difference between voltages on individual branches, than:

Vdiff = V1 - V2 = Zodd * (I1 -I2), and since I1 = -I2 = I, than:
Vdiff = Zodd * 2 * I = 2*Zodd * I

Therefore:

Zdiff = 2*Zodd = 2*Ö[(L – Lm)/(C + 2Cm)] (4)

Comparing Zodd expression (3) to the characteristic line impedance for a single ended line Zse = Ö(L/C) it is easy to notice that Zodd < Zse. That may be assessed intuitively as well. If two lines are coupled a current will exist between these lines in addition to the current between the line and reference plane and since for the same signal voltage level the current is higher, therefore, the line impedance is the lower. If we move the branches of differential line far away from each other, so the Lm = 0 and Cm = 0, then Zodd = Zse = Ö(L/C) and Zdiff = 2* Zse = 2*Ö(L/C), which is also a valid way to construct a differential line in some circumstances.

Lumped Parameter on Transmission Line

I am often asked questions related to variations and non-uniformities in characteristic impedance of the signal traces on PCB.

Considering that all high-speed differential interfaces are defined in specifications and standards these documents may have useful information for the design of various deviations, like connectors requirements or return loss of the packages. With increase of the signal bandwidth the PCB structures that could be neglected at lower data rates have become quite important. For example, the parameters of the packages should be considered (and very often the models of ICs do not include them). Or the PCB area under packages and connectors (breakout areas) are so densely populated with vias that traces routed in this area may have parameters quite different than in the free routing area. Another example of such deviations could be a via in a trace for transitions between different layers. When we are dealing with data rates above 3 Gbps the accurate analysis of these deviations is imperative. For the lower data rates the interface analysis may utilize a simplified approach replacing the actual line characteristics with lumped parameters like capacitance or inductance or if needed by impedance variation.

Of course the proliferation of signal integrity simulation tools allows an engineer to incorporate the lumped parameters into the model and verify the effect of these parameters. However, sometimes an engineer may want to understand the reason for the behavior of certain structure in order to determine the course of actions. Quite often one may want to understand what kind of parameter may cause certain signal behavior. For example, an engineer may want to figure out the effect of adding via capacitance or adding some inductance by clearing the reference plain around via and so on. Another situation may call for a quick analysis without a simulation tool or verification of simulation tool performance. In all these cases it may be beneficial to understand how to calculate an addition of small lumped parameters to an interface line.

Let us consider an example of addition of extra capacitance in the middle of the trace. Adding it at one of the line ends is too simple because the parameters of addition are just added to the lumped circuit parameters of driver or receiver.

To begin with we may check the reflection coefficient of this transmission line with added lumped parameter C and its effect upon the signal. Using the Laplace transform it is easy to show that:

r(s) = (1/sCIIZ₀) – Z₀)/(1/sCIIZ₀) + Z₀) = – s/(s + 2/CZ₀)

Consider an incident signal ramp: V_i(t) = (V/t_r)[t*U(t) – (t-t_r)*U(t-t_r), which may be expressed using the Laplace transform as: V_i(s) = V/t_rs² – Ve^-trs/t_rs² = (V/t_rs²)*(1 – e^-trs)

Where:
II – defines parallel circuits, for example: 1/sCIIZ₀ means value of capacitor parallel to transmission line impedance
t – time domain argument
s – Laplace transform argument
C – lumped capacitance
Z₀ – characteristic impedance of the line
V – amplitude of the incident wave
t_r – transition time
U(t), U(t-t_r) – unity functions
V_i(t) – incident signal
V_r(t) – reflected signal

Therefore, the reflection amplitude may be estimated as:

V_r(s) = r(s) * V_i(s) = –(V/t_r)*[s/(s + 2/Z₀C)]*(1/s²)*(1 – e^-trs)] =

–(V/t_r)/[s(s + 2/Z₀C)]+(V/t_r)*e^-trs/[s(s + 2/Z₀C)]

Using the inverse Laplace transform:

L^-1{–(V/t_r)/[s(s + 2/Z₀C)]} = V*(Z₀C/2t_r)*[e^–(2/Z0C)*t – 1]

L^-1{(V/t_r)*e^-trs/[s(s + 2/Z₀C)]} = –V*(Z₀C/2t_r)*[e^{–(2/Z0C)*(t-tr)} – 1]

Therefore:

V_r(t) = V(Z₀C/2t_r)*[e^{–(2/Z0C)*tu(t)} – e^{–(Z0/2C)*(t-tr)u(t-tr)})]

The result has shown a small negative pulse, which those who are used to deal with Time Domain Reflectometry (TDR) measurements may recognize for the case of additional capacitance on the line. This pulse will be added to the edge of the incident signal and affect the rise time of the signal that, of course, will be seen as an additional deterministic jitter.

Similar analysis methodology may be used if additional inductance or combination of inductance-capacitance-resistance is added anywhere on the line. Of course, I am using the Laplace transforms just as a convenient way to simplify the differential equations (and transform tables are readily available). Other solution methods are equally usable.

As it was mentioned above this analysis is a simplified method that is sufficient to the applicable data rates and it may allow engineer a quick evaluation of the effect of any circuit addition to the transmission line. Of course, the topic of how to determine the parasitic lumped parameters added to the line is not covered in this paper.

Series Resistor Analysis

It may not be widely recognized but hardware design engineers have encounters with signal integrity or SI issues practically on a daily basis.

On one of recent projects I have encountered a line termination application that is slightly different from usual techniques. The usual ones, like pull-ups and Thevenin equivalent circuits at the end of interface line or series resistors next to driver, are well understood. But the Micron Technology Application Note TN-46-14 has the following line termination recommendation for DDR memory data line termination: "For bidirectional I/O signals, such as DQ (Data line – M.G.), minimize ringing, overshoot, and undershoots by placing the R_S halfway between source and sink devices." That configuration is shown in Figure 1.

Figure 1. Resistor in the middle of the line

So… let us look why and how this approach works. The purpose of the series termination resistor is to reduce the value of the signal amplitude and rely upon reflection from the end of the line to bring the signal back into the range appropriate for receiver. The lower amplitude is beneficial for limiting reflections, crosstalk and emissions. The series resistor in the middle of the line is supposed to imitate the performance of a typical application when series resistor is placed close to the driver and, therefore, we should compare these two cases.

Figure 2. The typical case of series resistor is very close to the driver

The series resistor immediately after the driver, as shown in Figure 2, increases the driver's output resistance value and thus reduces the signal amplitude at point A calculated from the voltage divider generated by resistances R_out+R_s and Z:
V_A = V · Z/( Z + R_out + R_s) (1)

In the case of the resistor in the middle of the line, as shown in Figure 1, the point C is in the same position (in front of transmission line segment before receiver) as the point A in Figure 2. Therefore, we should compare the signal amplitudes at these points.
Let us consider the middle of the line case. The circuit configuration as seen from the point A is similar to one in the Figure 2 but without the series resistor R_s. Therefore:
V_A = V · Z/(Z + R_out) (2)

After the point A the signal with amplitude V_A traverses the transmission line to the point B (see Figure 3). It reflects from the point B, where Reflection Coefficient is:

r = [(Z+R_s)-Z]/[(Z+R_s)+Z]

Therefore, the signal amplitude at point B is:
V_B = V_A · [1 + r] = V_A · {1 + [(Z+R_s)-Z]/[(Z+R_s)+Z]} = V_A · 2(Z+R_s)/(2Z+R_s) (3)

Figure 3. Transmission line discontinuity

The signal amplitude at point C may be calculated from the divider as it is shown in Figure 4:
V_C = V_B · Z/(Z + R_s) (4)

Figure 4. Voltage divider created by series resistance and transmission line impedance

Combining the expressions for V_A, V_B and V_C we obtain the expression for V_C as a function of the input value V:
V_C = V · Z/( Z + R_out + R_s/2 + R_outR_s/2Z) (5)

As it could be seen comparing the expressions (5) and (1) the R_s
member of denominator in expression (1) is replaced by the (R_s/2 + R_outR_s/2Z ) in (5). That difference may show us the effect of moving the series resistor from the position near the driver to the middle of the transmission line.

The effect of the change clearly depends on the value of driver's output impedance. Consider that R_out of a high-speed transmitter circuit is relatively low. As a rule it is much lower than the value of line characteristic impedance that typically ranges between 45 Ohms and 65 Ohms. Therefore, depending on the value of R_out in respect to Z the range of the signal amplitude at point C varies between: V_C = V · Z/( Z + R_out + R_s/2) for R_out
approaching 0, which is slightly larger than V_A in (1), and V_C = V · Z/( Z + R_out + R_s) for R_out = Z, which is the same as V_A in (1).

The analysis shown above is beneficial in several ways:

• it shows that the series resistor placed in the middle of the transmission line does perform its duty of signal amplitude reduction
• it provides engineer with methodology to calculate the series resistor value
• it also shows the generic approach toward analysis of the high-speed interfaces with series termination resistors